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Espressif Systems /ESP32-S3 /APB_SARADC /CTRL2

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Interpret as CTRL2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SARADC_MEAS_NUM_LIMIT)SARADC_MEAS_NUM_LIMIT 0SARADC_MAX_MEAS_NUM 0 (SARADC_SAR1_INV)SARADC_SAR1_INV 0 (SARADC_SAR2_INV)SARADC_SAR2_INV 0 (SARADC_TIMER_SEL)SARADC_TIMER_SEL 0SARADC_TIMER_TARGET0 (SARADC_TIMER_EN)SARADC_TIMER_EN

Description

configure apb saradc controller

Fields

SARADC_MEAS_NUM_LIMIT

enable apb saradc limit the sample num
SARADC_MAX_MEAS_NUM

max conversion number
SARADC_SAR1_INV

1: data to DIG ADC1 CTRL is inverted, otherwise not
SARADC_SAR2_INV

1: data to DIG ADC2 CTRL is inverted, otherwise not
SARADC_TIMER_SEL

1: select saradc timer 0: i2s_ws trigger
SARADC_TIMER_TARGET

to set saradc timer target
SARADC_TIMER_EN

to enable saradc timer trigger

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data